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Altera_Forum
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14 years ago

source synchronous interface or virtual clock?

My FPGA is connected to an ADC. There are three interface signals between them : SCLK and DOUT, which are outputs from FPGA, and DIN, input from ADC. SCLK is generated by dividing the system c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The path to sclk is relevant on both sides, so you want to constrain the output source-synchronous style. For the input, you also use sclk as the set_input_delay -clock option, where the -max and -min are the longest and shortest round-trip delay from the time sclk leaves the FPGA to data coming back.

What is the clock rate? I've never heard of an ADC not sending a clock with its data. I assume it is quite slow, as that's not a very fast way to make an interface.