Contributor
Regular ContributorHI,
There is Intel MAX 10 High-Speed LVDS I/O User Guide: https://www.intel.com/content/www/us/en/programmable/documentation/sam1394433606063.html#sam1394435208308 available to handle the high-speed ADC interface.
Regards.
ContributorI am a bit confused by your response. The SERDES is used to basically do a serial to parallel conversion on parallel data streams. In the case in the original post, the scenario is a parallel 12-bit source synchronous transfer. Xilinx has documentation on how to deal with this issue and use low level primitives blocks like IOBUF, IDELAY e.t.c. Therefore, it was natural for me to see how such buffers can be instantiated in Altera/Intel FPGA code. I then found that the ALTDDIO_IN, ALTDDIO_OUT and ALTIOBUF exist in Cyclone V but not MAX 10. This gave me the impression that source synchronous input of ADC will not work with the MAX 10.
The document your mentioned says that Max 10 implements SERDES in LEs. OK, but how does that related to the original problem I have mentioned about?
