Occasional ContributorSource Synchronous between 2 Altera FPGA
Hi
I'm using the Methodology described at " AN 433: Constraining and Analyzing
Source-Synchronous Interfaces " and in the web course "
and I want to use (if possible ) the Setup and Hold output constraints . (Slide 31 in the course )
or System-Centric constraint approach
my system is 2 FPGA connected Stx10M - source-synchronous -SDR (15Mhz) (via DIB bypass) or Via Cables - I don't think it matters in this case .
for the output delay
what I'm looking for is the T-Setup and T-Hold of the "down-stream" FPGA ? where can I get the value ?
is it the pure Tsu / Thold of the Input Resgister in the Down-Stream FPGA ? or I should retrieve it by any timing report ?
a similar question goes to the Input Delay Values
where can I get the values Tco(Min/Max) (Slide 15 - in the course) of the External Device (which in my case is the again Stx10M) is it calculated value from timing report ? or is it simple the Tco of any Register in Stx10M
Thanks
Or.
Hi.
1) Should be good enough for DIB interface. Probably needs to take the DIB Latency into consideration as well check this https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/timing-transfer-for-bypass-mode.html and this https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/latency.html
2) Yes, Intel recommendation in "Source-Synchronous" methodology took into account the IO delay for the values of the T-hold / T-setup only for the register. External IO and Cable /PCB connection between the FPGA probably will need to take into account the extra latency.
Thanks,
Best Regards,
Sheng
