Forum Discussion
Occasional ContributorSource Synchronous between 2 Altera FPGA
Hi.
1) Should be good enough for DIB interface. Probably needs to take the DIB Latency into consideration as well check this https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/timing-transfer-for-bypass-mode.html and this https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/latency.html
2) Yes, Intel recommendation in "Source-Synchronous" methodology took into account the IO delay for the values of the T-hold / T-setup only for the register. External IO and Cable /PCB connection between the FPGA probably will need to take into account the extra latency.
Thanks,
Best Regards,
Sheng
Occasional ContributorHi
it seems it T-hold/T-setup are not simple to find the values - as far as I understand it is tightly coupled to the IO supply / IO configuration
therefore Intel provided the next process .
I did the process , and I understand the Th / Tsetup values added IO to Register trace values / and impact by the IO supply/configuration .
therefore I left with 2 gaps :
1) is it good enough for DIB interface (which does not have the IO. (connecting 2 dies of Stratix 10M)
if not , from where can I get the real values ?
2) in case I use External IO and Cable /PCB connection between the FPGA does Intel recommendation in "Source-Synchronous" methodology took into account the IO delay for the values of the T-hold / T-setup . or the values should be only for the register only ?
Or.
