Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorsorter in vhdl
hi every one
i want avhdl code to sort integer input ascending if i have an array such as 1,8,9,7,2 the out put will be such as 1,2,7,8,9 i search a lot but didn't find any code that helping me thanks .40 Replies
Altera_Forumyou know , you are a great man
i want to thank you very much for helping me but, why the first input becoming the first output whereas should be the last output ???- Altera_Forum
I gave you a Guide and left details for you to manage. It is not in your interest to hand you a finished work.
However, this time I will correct my latency issue, see code below). You can do a further modification if you want to get rid of zero data and interrupted read by reading into two further rams. one for code and one for duration, both rams addressed by counter that increments only if non zero data arrives... then finally read out both rams from 0 to count value.library ieee; use ieee.std_logic_1164.all; use IEEE.numeric_std.all; entity bubblesort is port( clk : in std_logic; we : in std_logic := '1'; trigraph : in std_logic_vector(7 downto 0) := x"0F"; duration : in integer range 0 to 1023 := 5; read : in std_logic := '0'; dout : out std_logic_vector(7 downto 0) ); end entity; architecture rtl of bubblesort is signal address, rd_addr : integer range 0 to 1023 := 0; signal trigraph_d : std_logic_vector(7 downto 0); signal we_d : std_logic := '0'; type mem is array(0 to 1023) of std_logic_vector(7 downto 0); signal ram : mem := ((others=> (others=>'0'))); begin --infer ram process(clk) begin if(rising_edge(clk)) then dout <= ram(address); if(we_d = '1') then ram(address) <= trigraph_d; end if; end if; end process; process(clk) begin if rising_edge(clk) then we_d <= we; trigraph_d <= trigraph; if read = '1' then if rd_addr < 1023 then rd_addr <= rd_addr + 1; end if; end if; if read = '0' then address <= duration; else address <= rd_addr; end if; end if; end process; end rtl; - Altera_Forum--- Quote Start --- You can do a further modification if you want to get rid of zero data and interrupted read by reading into two further rams. one for code and one for duration, both rams addressed by counter that increments only if non zero data arrives... then finally read out both rams from 0 to count value. i try to modify the code it is as you suggest kaz
library ieee; use ieee.std_logic_1164.all; use IEEE.numeric_std.all; entity bubblesort is port( clk : in std_logic; we : in std_logic := '1'; trigraph : in std_logic_vector(7 downto 0) := x"0F"; duration : in integer range 0 to 1023 := 5; read : in std_logic := '0'; code : out std_logic_vector(7 downto 0) ); end entity; architecture rtl of bubblesort is signal address, rd_addr : integer range 0 to 1023 := 0; signal trigraph_d,dout : std_logic_vector(7 downto 0); signal we_d : std_logic := '0'; signal N : integer := 0; type mem is array(0 to 1023) of std_logic_vector(7 downto 0); signal ram : mem := ((others=> (others=>'0'))); begin --infer ram process(clk) begin if(rising_edge(clk)) then dout <= ram(address); if(we_d = '1') then ram(address) <= trigraph_d; end if; end if; end process; process(clk) begin if rising_edge(clk) then we_d <= we; trigraph_d <= trigraph; if read = '1' then if rd_addr < 1023 then rd_addr <= rd_addr + 1; end if; end if; if read = '0' then address <= duration; else address <= rd_addr; end if; end if; end process; ------discard zero values process(read,dout) begin if read = '1' then if dout /= "00000000" then N <= N + 1; code <= dout; end if; end if; end process; end rtl; - Altera_Forum
or that modification is right
i hope you advise melibrary ieee; use ieee.std_logic_1164.all; use IEEE.numeric_std.all; entity bubblesort is port( clk : in std_logic; we : in std_logic := '1'; trigraph : in std_logic_vector(7 downto 0) := x"0F"; duration : in integer range 0 to 1023 := 5; read : in std_logic := '0'; dout : out std_logic_vector(7 downto 0) ); end entity; architecture rtl of bubblesort is signal address, rd_addr : integer range 0 to 1023 := 0; signal trigraph_d : std_logic_vector(7 downto 0); signal we_d : std_logic := '0'; signal dout_buf : std_logic_vector(7 downto 0) := x"ff"; type mem is array(0 to 1023) of std_logic_vector(7 downto 0); signal ram : mem := ((others=> (others=>'0'))); begin --infer ram process(clk) begin if(rising_edge(clk)) then dout <= ram(address); if(we_d = '1') then ram(address) <= trigraph_d; end if; end if; end process; process(clk) begin if rising_edge(clk) then we_d <= we; trigraph_d <= trigraph; if read = '1' then if rd_addr < 1023 then rd_addr <= rd_addr + 1; end if; end if; if read = '0' then address <= duration; else address <= rd_addr; end if; end if; end process; --discard zeros values process(clk) begin if(rising_edge(clk)) then if ram(address)/=x"00" then dout_buf <= ram(address); end if; end if; end process; dout <= dout_buf; end rtl; - Altera_Forum
you better keep ram inference clean.
use your same extra logic on dout instead (making it internal readable signal first) - Altera_Forum--- Quote Start --- you better keep ram inference clean. use your same extra logic on dout instead (making it internal readable signal first) --- Quote End --- how can i do that ??? plz ,plz kaz there isn't any one help me except you
- Altera_Forum
hi sorry to bump an old thread but i had a question regarding the entity..
entity bubblesort is port( clk : in std_logic; we : in std_logic := '1'; trigraph : in std_logic_vector(7 downto 0) := x"0F"; duration : in integer range 0 to 1023 := 5; read : in std_logic := '0'; dout : out std_logic_vector(7 downto 0) ); end entity; why := x"0F"; in this line trigraph : in std_logic_vector(7 downto 0) := x"0F"; and := 5; in the following duration : in integer range 0 to 1023 := 5; thanks in advance - Altera_Forum
Those are default assignment - if they are left unconnected when the entity is instantiated, they will be assigned those default values instead of being left open.
- Altera_Forum
Okay thanks for the reply. so similar to trigraph[0], trigraph[1]------trigraph[7] = 0x0F; in C code ? but why this init value? and not 0x0E or any other value. ?
- Altera_Forum
Hi again im tyring to add the sorting algorithm to my IP Catalog in Qsys, but get some errors regarding burstcount,readdatavalid and waitrequest. Also Clock and reset must be associated with interface. Being new to FPGA and the Altera environment i cant seem to locate where to change this. Any help would be appreciated.
https://www.alteraforum.com/forum/attachment.php?attachmentid=10772
