sorter in vhdl

i try to write this code

is it as you suggest kaz

library ieee;

use ieee.std_logic_1164.all;

use IEEE.numeric_std.all;

entity bubblesort is

port(

clk : in std_logic;

we : in std_logic;

trigraph : in std_logic_vector(7 downto 0);

duration : in integer range 0 to 1023 ;

rd_duration : in integer range 0 to 1023;

rd_trigraph : out std_logic_vector(7 downto 0)

);

end entity;

architecture rtl of bubblesort is

type mem is array(0 to 1023) of std_logic_vector(7 downto 0);

signal ram : mem := ((others=> (others=>'0')));

signal n,i : integer range 0 to ram'length;

begin

process(clk)

begin

if(rising_edge(clk)) then

if(we = '1') then

n <= 0;

i <= 0;

ram(duration) <= trigraph;

end if;

end if;

if(rising_edge(clk)) then

if (we= '0') then

rd_trigraph <= ram(rd_duration);

end if;

end if;

if (n < ram'length) then

if (i < ram'length-1) then

if (ram(i) > ram(i+1)) then

ram(i) <= ram(i+1);

end if;

i <= i+1;

else

i <= 0;

n <= n+1;

end if;

end if;

end process;

end rtl ;