SOPC/Quartus II "pass through component" problem

Hi Everybody,

I have Quartus 9.0 running on Cyclone III Board with Bitec's HSMC DVI daughterboard on it.

I have Clocked Video Input (1080p60 DVI input) and Clocked Video Output (1080p60 DVI output). I want to add a dummy component in between my input and output.

At the beginning it will just pass through whatever comes by it, later on I am planning to do some easy XORing operations on the frame I am receiving.

In SOPC, I created my "pass through" component with all the necessary signals and added it in between CVI and CVO. It generates in SOPC without problems and it compiles on Quartus II, as well.

Now the question is how to make these 3 components communicate with each other so that I can have a smooth transition of my input through my custom "pass through component" and then to the output.

I believe that I should write Verilog code using "clk, reset, data, ready, valid, starofpacket, endofpacket" signals but I think I need a jump start.

Can someone tell me how to start this process of communicating my components with each other ?

Thanks a lot in advance ,

Tyler