SOPC/QSYS connect 32 bits avalon slave to a 8 bits SRAM

Unfortunately for you the Nios always asserts all 4 byte enables for reads.

So there is nothing that external fabric can do to support byte reads from 8-bit memory.

I'm surprised about what you are seeing for writes. I though the bus width adapter always generated all four cycles, but generated some of them without the byte enable asserted.

Writes could, of course, be 'posted' and processed in the following clock cycles. That would help with some access patterns.

It would help even more if the nios cpu itself had a build option to do posted writes.

Posting writes and assserting the byte enables for Avalon reads should really be reasonably straight forward modifications.

I can think of a couple of ways of doing byte accesses - neither is very nice:

1) Map the memory so that high address lines force byte only accesses.

2) Access it through a clocked custom instruction rather than as an avalon slave.