SOPC/QSYS connect 32 bits avalon slave to a 8 bits SRAM

hi it's me again

8 bits avalon MMslave seems to work, but not optimized for speed

i verified all access types using my oscilloscope, trigged on the falling edge of the chip select signal

writes :

1> a char takes 1 write cycle.

2> a short int takes 2 write cycles. a short integer needs to be "2 bytes aligned" in memory

3> a int takes 4 write cycles. a short integer needs to be "4 bytes aligned" in memory

read :

1> a char takes 4 read cycle. the address bus spans all 4 bytes of a "4 bytes aligned" location in memory, and the NIOS selects the first, second third or fourth byte depending on the location of the byte that you need to read for

2> a short int takes 4 read cycle. same as above. the nios selects the first or the last two bytes. short int must be "2 byte aligned"

3> a int takes 4 read cycle. int must be "4 bytes aligned"

how do i create an avalon MM slave that allows reading times to be just as the same as the writing times ?

do i need to use byte enables ?

THANK YOU FOR HELPING

Best regards

Alban