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Altera_Forum
Honored Contributor
17 years agoSOPC ERROR: Cannot have an associated clock
Hi, I'm trying to generate a SOPC component from a VHDL file. I want to make an I2C component. The VHDL basis ist the I2C Master/Slave from opencores. I modified it in that way, that I only nee...
Altera_Forum
Honored Contributor
17 years agoTraditionally you have two ways oy handling timing on an avalon slave interface.
The first way is to use fixed timing. In that case you only use the read and write signals, with no acknowledge, and you specify in the component builder how many cycles are necessary for a read or a write operation. The other one is to use the waitrequest signal. In that case, as soon as you have the read or write request, you assert waitrequest, and the master will wait. When the read or write operation is finished, de-assert waitrequest. I guess this is the closest to the acknowledge that you want to implement. All this is well described in the avalon interface specification (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf).