Forum Discussion
Altera_Forum
Honored Contributor
16 years agoThe second part of the signal name should be the interface name, and should be the same for all the signals in one interface. In your case you could use those signal names:
--INPUTS
csi_sysclk_clk : IN std_logic; -- The signals obey the naming conventions specified in the Quartus II Handbook Volume 4: SOPC Builder
csi_sysclk_reset : IN std_logic;
avs_avalon_read : IN std_logic;
avs_avalon_write : IN std_logic;
avs_avalon_begintransfer : IN std_logic;
avs_avalon_writedata : IN std_logic_vector (7 DOWNTO 0);
--OUTPUTS
coe_i2c_sda : INOUT std_logic;
coe_i2c_scl : INOUT std_logic;
avs_avalon_readyfordata : OUT std_logic;
avs_avalon_readdata : OUT std_logic_vector (7 downto 0); -- Field 0 contains the acknowledge information
avs_avalon_dataavailable : OUT std_logic
I'm not sure you need all the begintransfer, readyfordata and dataavailable, but it depends on how you do your IP. Not everything is picked up by the component editor, you'll at least have to declare manually the export signals, and maybe associate the avalon interface with the correct clock.