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Altera_Forum
Honored Contributor
Honored ContributorSOPC, Custom IP (Pass through) problem
Hi Everybody,
I have quartus 8.0 running on cyclone iii Board with bitec's hsmc dvi daughterboard on it. I have clocked video input (1080p60 dvi input) and clocked video output (1080p60 dvi output). I want to add a dummy component in between my input and output. At the beginning it will just pass through whatever comes by it, later on I am planning to do some easy XORing operations on the frame I am receiving. What I did was, I clicked on "Create new component" and used different templates to start with such as Avalon M-M Slave/Master, Avalon St-Sink/Source and added all the signals to it like, clk, reset, data, ready, valid, starofpacket, endofpacket. Regardless of which template I use, it always gives me the same error message : "the connection point has only some of the required packet signals" I am a newbie, so I am obviously forgetting to add some signals which are necessary for my custom component to communicate with Clocked video in an out but I don't know what I am missing. Can someone please guide me ? Thank you so much in advance , Tyler PS:I don't have the vhdl or verilog code for my custom component.14 Replies
Altera_ForumAs I said before, you have to hold the <Shift> key while you click the "Generate" button to override the errors.
Jake- Altera_Forum
Thank you formjk and Jake for your clear and fast responses. I did what you guys told me but SOPC doesn't allow me to generate. it says "Error: Generation skipped because the system has validation errors."
I am adding the screenshots of what I have been doing so far. Basically I added Avalon Streaming Source and Avalon Streaming Sink for my custom component in order to be able to handle the high throughput of clocked video input and output. I am not entirely sure if I am doing everything correctly, can you guys double check my design through the screenshots and let me know if there is any part that is not compatible for whatever reason ? I would highly appreciate that. PS: Once again my goal is first creating a pass through component between DVI clocked video input an DVI clocked video output. Once the SOPC generates I think I should start writing the verilog code to do the XORing operation. Thanks a lot in advance, Tyler - Altera_Forum
formjk is correct. The empty signal is the problem. However, it's not your fault. The Video IP cores do not use the empty signal, but SoPC builder expects it to be there for everything else. It's actually called out in the Errata.
You can get around it by: 1 - Don't create the empty signal for your custom core. When you want to create the core, hold the <Shift> key as you click create. 2 - Do create the empty signal. In which case you'll get an error in SoPC builder when you connect up the component. Hold the <Shift> key when you click the generate button in SoPC builder. 3 - Upgrade to 8.1 or 9.0. Altera fixed the problem in 8.1. Jake - Altera_Forum
have you added "empty" signal ?
Also, i am not sure if you can create a component without a verilog/vhdl code. may be as of now you can just create a verilog/vhdl module with just the port declaration and no logic inside.
