SOPC builder ERROR: peripheral controlled wait ... What it means??

I add an user logic module with avalon-mm slave interface and conduit interface in the sopc builder and when "generat", it gives errror at end signed:

***:peripheral controlled wait not supported for peripheral with non-zero setup and /or hold times 255

I know this is caused by the "waitrequest" signal in the mm-slave interface which i used but what can i do with this??

the VHDL of the module like this(just used to transform the dataread and datawrite into a bir-direction dataRW):

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--This file is for avalon_MM slave interfacing test

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

--end of library decleration

-----------------------------------------------

entity No_clk_avalonMM_slave_adpter is

--entity name should be the same as the VHDL project name

port

(

CSn_from_MM: in std_logic:='Z';

RDn_from_MM: in std_logic:='Z';

WRn_from_MM: in std_logic:='Z';

dataW_from_MM: in std_logic_vector(15 downto 0):=(others=>'1');

dataR_to_MM: out std_logic_vector(15 downto 0):=(others=>'1');

ADDR_from_MM: in std_logic_vector(15 downto 0):=(others=>'Z');

ByteSL_from_MM: in std_logic_vector(1 downto 0):=(others=>'Z');

waitrequest_to_MM: out std_logic:='Z';

--CLK_from_MM: in std_logic:='0'; --avalon CLOCK

CSn_to_PHY: out std_logic:='1';

RDn_to_PHY: out std_logic:='1';

WRn_to_PHY: out std_logic:='1';

ADDR_to_PHY: out std_logic_vector(15 downto 0):=(others=>'Z');

ByteSL_to_PHY: out std_logic_vector(1 downto 0):=(others=>'Z');

BUSYn_from_PHY: in std_logic:='0';

DATA_fromto_PHY: inout std_logic_vector(15 downto 0):=(others=>'Z')

);

end No_clk_avalonMM_slave_adpter;

-----------------------------------------------

architecture slave2phy of No_clk_avalonMM_slave_adpter is

signal temp4MM_W: std_logic_vector(15 downto 0);

begin

CSn_to_PHY<=CSn_from_MM;

RDn_to_PHY<=RDn_from_MM;

WRn_to_PHY<=WRn_from_MM;

ADDR_to_PHY<=ADDR_from_MM;

ByteSL_to_PHY<=ByteSL_from_MM;

waitrequest_to_MM<=BUSYn_from_PHY;

process(WRn_from_MM,RDn_from_MM,DATA_fromto_PHY)

begin

if(CSn_from_MM='0')then

if(WRn_from_MM='0' and RDn_from_MM='1')then

DATA_fromto_PHY<=dataW_from_MM; --AVALON MM write data to the peripheral

dataR_to_MM<=(others=>'Z');

elsif (RDn_from_MM='0' and WRn_from_MM='1')then

DATA_fromto_PHY<=(others=>'Z'); --prevent the INOUT port datastream loop!!!!!

dataR_to_MM<=DATA_fromto_PHY; --AVALON MM read data from the peripheral

else

DATA_fromto_PHY<=(others=>'Z'); --uncertain status!

dataR_to_MM<=(others=>'Z');

end if;

else

DATA_fromto_PHY<=(others=>'Z'); --uncertain status!

dataR_to_MM<=(others=>'Z');

end if;

end process;

end slave2phy;

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