Forum Discussion
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- I don't think the trouble is in your HDL code. Is this a new component or are you trying to upgrade it from an existing component? The error would indicate that you've specified read and/or write wait times of something other than zero in the component wizard. --- Quote End --- Hello! Yes I made an update form this VHDL file, first there is no "waitrequest" and i define the read/write time in the SOPC builder, there is no erro. Then when i added the "wait" signal, the read/write definition window become gray(I can define nothing there). and then when I push generat, the error appear.