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Altera_Forum
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15 years ago

SOPC and beginbursttransfer

I am creating a custom Avalon MM Master that will need to speak to a HPCII DDR2 controller. Rather than generating the core in the SOPC tool, we are generating it using the Megawizard in Quartus. ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

This thread is pretty old, but since I'm having the same problem and I see no solution, I'll resurrect it:

pinscore said that he generated the ddr2 controller via megawizard (read - outside of sopc or qsys). Therefore, the exported signals from sopc and the ddr2 controller are joined in HDL. But the exported signals do not include beginbursttransfer, and the ddr2 controller needs it. Well, in my case, I'm using mpfe, which also needs it to work properly. So, how to tell sopc/qsys to generate it? Right now I'm using the "Avalon-MM Master Translator", but it seems like overkill. I was also considering generating it by it being a positive edge detector of (read or write), but I'm not sure if it would be correct.