some questions about RGMII timing constraints on Cyclone V GX development board

post_message -type info "Reading file: \'rgmii_input.sdc\'"# **************************************************************# Input Delay Constraints (Center aligned, Same Edge Analysis)# **************************************************************

create_clock

-name virtual_phy_clk

-period $PERIOD_125//

set Tco_max 0.350

set Tco_min -0.350 /// negative value ????????? I can't understand!!!

set Td_max 1.0

set Td_min 0.9

set longest_src_clk 0.0

set shortest_src_clk 0.0

set longest_dest_clk 1.0

set shortest_dest_clk 0.9

set Tcs_largest [expr $shortest_dest_clk - $longest_src_clk]# =0.9-0.0=0.9

set Tcs_smallest [expr $longest_dest_clk - $shortest_src_clk]# =1.0-0.0=1.0

set IMD [expr $Td_max + $Tco_max - $Tcs_largest]# =1.0+0.350-0.9=0.45

post_message -type info "Input Max Delay = $IMD"

set ImD [expr $Td_min + $Tco_min - $Tcs_smallest]# =0.9+(-0.35)-1=-0.45

post_message -type info "Input Min Delay = $ImD"# Constraint the path to the rising edge of the phy clock

set_input_delay -add_delay -clock virtual_phy_clk -max $IMD [get_ports {enet_rx_dv enet_rx_d*}] // not the enet_rx_clk,but a virtual clk,why ??? I can't understand the virtual clock ??

set_input_delay -add_delay -clock virtual_phy_clk -min $ImD [get_ports {enet_rx_dv enet_rx_d*}]# Constraint the path to the falling edge of the phy clock

set_input_delay -add_delay -clock virtual_phy_clk -max -clock_fall $IMD [get_ports {enet_rx_dv enet_rx_d*}]

set_input_delay -add_delay -clock virtual_phy_clk -min -clock_fall $ImD [get_ports {enet_rx_dv enet_rx_d*}]