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Altera_Forum's avatar
Altera_Forum
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8 years ago

Some questions about intel HLS RTL design.

Hello. I am currently testing RTL design using Intel HLS. There are a number of errors that occur during HLS compilation and RTL conversion, but the error seems to lack work around or guide...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

1. HLS generates handshaking logic to interface with the rest of your system. In addition to the parameters you specify, it generates a component invocation interface containing the start/busy and done/stall signals.

2. You can use the hls_always_run_component attribute to disable the handshaking logic (Can check in RTL viewer): 


hls_always_run_component
component float add_fp_tiger(float a, float b) {
    float p;
    p = a + b;
    return p;
}  // test the scalar addition within hard-FP

Note that with the handshaking logic disabled, you cannot use the co-simulation flow to validate your component (like Xilinx).

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)