Some questions about intel HLS RTL design.

Hello.

I am currently testing RTL design using Intel HLS. There are a number of errors that occur during HLS compilation and RTL conversion, but the error seems to lack work around or guide.

I'd like to ask you a few questions about this difficulty. This includes questions about HLS optimization errors and their own concepts.

- Is the intel HLS software for creating one independent RTL IP?

- Does a verilog top design with multiple sub-modules(instances) need to be designed manually? (I don't need to use SOPC or SOC. So, I also don't consider Qsys to design)

- Is it possible to obtain a generic sequential RTL design with HLS that does not include an Avalon interface? What is the exact purpose of the hls_always_run_component?

- The user manual says that the HLS/matrix_mult.h library for matrix multiplication is provided, but where is it located? Not found in Quaruts 17.1 standard and lite in use.

- Where can I find the meaning of error messages generated when converting the FPGA?

I got an error : Call parameter type does not match function signature! What does this mean?

Here's a code structure I've created. Please give me a lot of advice.

code: main.cpp

float (*function1(x,x,x))[3] {}

float (*function2(x,x,x))[3] {}

float (*function3(x,x,x))[3] {}

component float (*aaa())[2] {

float (*y1)[3] = function1(x,x,x);

float (*y2)[3] = function1(y1,x,x);

....

return y9;

int main() {

float (*aaa_out)[2] = aaa();

printf("%f\n", aaa_out[0][0]);

...

return 0;

}