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Altera_Forum
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17 years ago

Some glitches in the simualtion waveforms

Hi, Experts, I met a problem in my VHDL code. My algorithm is to cut in the deadtime in the incoming PWM signals and output them. I have 6 incoming PWM signals to switch 6 IGBTs. So, these 6 p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Despite the latch warnings, I don't see anything in the RTL Viewer that would cause glitches on po1_PWM_Bot1. This output probably isn't glitching at all but having normal behavior of a register changing only at its input clock edges. Zoom in on your simulation waveform till you can see the individual clock cycles. That should make it easier to make sense of what is happening on the signals.