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Altera_Forum
Honored Contributor
12 years agoThere is a new request in my system. The FPGA is EP4CE30. Now, we want to use a SPI flash for EP4CE30 for configuration. This SPI flash is connected directly to EP4CE30's AS port. During power-up, FPGA will read configuration data directly from this SPI flash. Then, we want to get ISP(In System Programable) function for FPGA configuration data. This function is used to download new configuration data into spi flash through RS-232 port or ethernet port. We have a processor which can get configuration data from RS-232 or ethernet port.
My question is: how to connect both the processor and FPGA to this SPI flash and avoid bus conflict at the same time? Or any other suggestions to implement ISP function?