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fogl's avatar
fogl
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Soft LVDS Serdes

I am reading the Soft LVDS documentation (UG-M10LVDS | 2017.12.15) and some things seems strange: The block diagram on Figure2 shows that two clock sources (slow and fast) should be connected to so...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi ,

Kindly find the inline answers

Point no: 1 >> Those fast and slow clocks can be seen from the timing report not from the from the parameter setting of the serdes IP

Reference page no: 33

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_lvds.pdf

Point no:2 > FCLK should be data rate frequency/2 , Where do you find the information.

Point no:3 > Intel FPGA does not recommend to write own logic for serdes, so do not have any documentation for the reference.