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ArjunBK's avatar
ArjunBK
Icon for New Contributor rankNew Contributor
4 years ago

Soft LVDS IP simulation for MAX10

Soft LVDS IP core - simulation Hello, I am working with Intel Max10 - 10M50DAF484C6GES for one of my applications, which has the requirement to transfer and rec...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

I am able to get the rx_out signal with your testbench and the settings that you mentioned.

Can you please try adding altera libraries during elaboration? You may use following command:

vsim -t ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm work.serdes_rx_tx_tb


Regards


ArjunBK's avatar
ArjunBK
Icon for New Contributor rankNew Contributor
4 years ago

Hello,

Thank you for the reply. I tried with the command that you have provided in tcl command window, i am getting error . I have attached the screen shot for your reference "command.jpg". I could add the libraries using GUI, Assignments-> settings-> library (i have attached the screen shot for the same "library.jpg") but i see no change in the wave form, still RX_out stuck at "0".