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YDu00's avatar
YDu00
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6 years ago

sof and pof behaves differently for Max 10

I am using 10M04 FPGA. for some of the versions of my RTL project, if I download SOF file, it works great. if I download POF, it works partially right. this happends on all 3 boards that I have. any...
YDu00's avatar
YDu00
Icon for New Contributor rankNew Contributor
6 years ago

Hi, John,

what I can observe is that register "read_offset " is not updating.

I am not able to debug more. Since If I simply add a signal tap logic analyzer to debug(not changing any RTL), this problem will disappear. I think due to the POF file got changed with the additional signal tap logic function.

So it is really hard to find out the reason. any netlist change will affect the POF file, and then will make this issue disappear.

my question is, After configuration is done, does the FPGA read back the configuration in the Logic element and compare with the original data in the flash to make sure the configuration is effective?