SODIMM RAM interfacing with FPGA

I dont know what is happening with the thread. So I am again posting it.

Hi, I am working on High Performance Computing in low cost FPGA. So I have bought DE0-Nano (Cyclone 4) and I want to interface a SO-DIMM RAM with that Board. Physically it is possible I think, because in the Terasic, I have found a board "Terasic TR5 FPGA Development Kit" which contains Stratix 5 GX (5SGXEA7N2F45C2N) FPGA and there is a socket of "DDR3 SO-DIMM" Memory, where u can plug upto 8GB of memory at a maximum speed of 933 MHz. If you seed the attached image, there you can see that DDR3 SO-DIMM memory sockets are connected with 64 pins of Stratix 5 GX FPGA though that Memory socket has 260 pins. So, I assume that we would require minimum 64 pins to connect a DDR3 SO-DIMM RAM to interface with FPGA. And in this context I can also say that DE0-Nano board has more than 80 GPIO Connections. So, It is physically possible to interface a DDR3 SO-DIMM RAM with DE0-Nano.

So, have any one has done this kind of work then kindly help me out. Any help will be appreciated.

Thanks In Advance.