It will not have touchscreen IP but that's something that can be added as soft logic in the FPGA. It's been a while since I've dealt with touchscreens but if things have not changed then they typically use a parallel bus with some protocol to control the pixels on the screen and the touch sensors are readable over a low pincount interface like I2C or SPI (which the SoC has dedicated IP for). To drive the pixels out you would need some sort of frame buffer hardware implemented in the FPGA fabric. You would want the lowest power SoC which is the Cyclone V SoC device.