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NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Slew Rate settings

Hello, I am using Quartus Prime STD 20.1.1. The device is Cyclone 10 FPGA: 10CL080YU484A7G. I see that in the pin planner there is only one option under Slew Rate settings as seen in the below s...
  • Farabi_Altera's avatar
    Farabi_Altera
    4 years ago

    Hi,

    the slow slew rate is not supported by all IO standard set to the GPIO pins. You need to use the IO standard which supports slow slew rate and set this IO standard to the GPIO pin you want to use.

    If you see the IBIS model, the IO standard with 's' at the last of their name, is slow slew rate, 'm' for medium slew rate and 'f' for fast slew rate:

    IBIS file for Cyclone 10 LP : https://cdrdv2.intel.com/v1/dl/getContent/674929

    regards,

    Farabi

Farabi_Altera's avatar
Farabi_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

the slow slew rate is not supported by all IO standard set to the GPIO pins. You need to use the IO standard which supports slow slew rate and set this IO standard to the GPIO pin you want to use.

If you see the IBIS model, the IO standard with 's' at the last of their name, is slow slew rate, 'm' for medium slew rate and 'f' for fast slew rate:

IBIS file for Cyclone 10 LP : https://cdrdv2.intel.com/v1/dl/getContent/674929

regards,

Farabi

Farabi_Altera's avatar
Farabi_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

best regards,

Farabi