It sounds like a simple design. Basically I suggest putting the logic together and building it..
Your DRAM controller will be the most complex piece of logic and what ever state-machine you have controlling it.
The MAX10 family is definitely capable of handling this requirement, but it's brand new so only the 8K LE and 50K LE devices are really available at this time. (The rest of the family will come out over the next year)
I guess the real question is what are you doing with the SDRAM. Are you planning on putting a small CPU in the FPGA? or are you gathering data from some other source? If so, how are you getting the data out?
If you can get the design to build, you can then target the various FPGA's and see how much space it really takes.
Then pick a family and device accordingly. Otherwise, pick the device you think it will fit it, go one size up for feature creep, and make sure you have one more size up available in the same package just in case.
Putting different sized devices in the same package is not always one-to-one. So before you layout the board, Double check all the pinouts to make sure device migration doesn't have any issues with the layout.
Pete