Single address Avalon MM slave

What has the width of the address bus got to do with this?

If you are accessing avalon slaves from a Nios cpu then you really want to make your slaves have a 32bit data interface - even if you ignore all the high bits and return zeros on reads.

If you have an 8bit slave then a 'bus width adapter' is inserted that converts the 32bit transfer into four 8bit ones with the byte enables set appropriately (ie 3 of the write requests won't have the byte enable asserted).

Reads by the Nios always assert all 4 byte enables.