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Honored Contributor
Honored ContributorSimulink IIR Bandpass filter on DE2
I made a filter with matlab simulink and used one of its tools to create vhdl code out of it. I implemented it on an FPGA and it gives me reasonable output except that the frequencies that it pass ar...
Altera_ForumHonored Contributor
Honored ContributorADCLRC seems reasoanable as a filter sampling clock. The results seem to indicate, that the actual clock frequency is different from calculated value.
The said 170 Hz looks like a 3rd harmonic, either caused by a distorted signal source, ADC overload or filter truncation errors (You didn't tell about relative amplitudes or the filter word length).
