New Contributor
Super ContributorHello
Welcome to INTEL forum. Could you try do reset sequence. Resetting the transceiver in an Intel Cyclone V FPGA involves a specific sequence to ensure proper initialization and operation.
Here are the steps to perform a reset sequence for the Cyclone V transceiver:
1. Assert the Reset Signals
- **Transceiver PLL Reset (pll_powerdown)**
- Assert the `pll_powerdown` signal to reset the Phase-Locked Loop (PLL).
- **Transceiver Digital Reset (rx_digitalreset and tx_digitalreset)**
- Assert the `rx_digitalreset` signal to reset the receiver digital logic.
- Assert the `tx_digitalreset` signal to reset the transmitter digital logic.
2. Wait for the Reset to Take Effect
- Hold the reset signals asserted for a sufficient amount of time to ensure that the internal logic and PLL have been properly reset. This typically involves waiting for a few clock cycles.
3. Deassert the Reset Signals in Sequence
- **Deassert PLL Reset**
- Deassert the `pll_powerdown` signal to release the PLL from reset.
- Wait for the PLL to lock. This can be checked using the `pll_locked` signal. Ensure that the PLL has achieved a stable lock before proceeding.
- **Deassert Digital Resets**
- Deassert the `rx_digitalreset` signal to release the receiver digital logic from reset.
- Deassert the `tx_digitalreset` signal to release the transmitter digital logic from reset.
Ensure that these signals are deasserted after the PLL has locked.
4. Verify Status Signals
- Check the status signals to ensure that the transceiver has properly initialized:
- `rx_freqlocked`: Indicates that the receiver PLL has locked to the incoming data frequency.
- `tx_freqlocked`: Indicates that the transmitter PLL has locked.
### Example Reset Sequence Timing
1. **Assert Reset Signals:**
- Assert `pll_powerdown`.
- Assert `rx_digitalreset`.
- Assert `tx_digitalreset`.
Wait for at least 10 clock cycles (the exact number may vary depending on your design requirements).
2. **Deassert PLL Reset:**
- Deassert `pll_powerdown`.
Wait for the `pll_locked` signal to go high, indicating that the PLL has locked. This can take several microseconds depending on the PLL configuration.
3. **Deassert Digital Resets:**
- Deassert `rx_digitalreset`.
- Deassert `tx_digitalreset`.
Check the `rx_freqlocked` and `tx_freqlocked` signals to ensure the receiver and transmitter have locked to their respective frequencies.
Refer to the Intel Cyclone V Transceiver User Guide and the specific design documentation for detailed information tailored to your application's requirements.
New ContributorHi,
Thank you for your response. I later found out that I need to transmit information from tx_parallel_data before the tx_serial_data automatically stops sending data to avoid unknown events.
For example, after deasserting tx_digitalreset, I need to continuously send synchronization signals /K28.5/ for a period before starting to send my data, instead of waiting for a while after deasserting tx_digitalreset before sending my data. Is this process correct?
