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Honored Contributor
Honored ContributorSimulation error when simulating PLL
Hello, I am using run time configurable PLL in my project containing Arria V FPGA. I need to vary the output frequency of the PLL at run time. I have written a logic for loading the N and M c...
Altera_ForumHonored Contributor
Honored ContributorReferring to the link you provided, you can issue (type) that 'vlog' command in ModelSim's Transcript window without needing to add it to a tcl script. However, the advantages of having your simulation captured in a tcl script are worth considering...
ModelSim requires the functional behaviour of the PLL. The support solution is simply pointing out that it can obtain these from either the vhdl or verilog libraries that come with Quartus. However, there is clearly an issue with ModelSim and compiling the vhdl libraries. Hence, the solution's suggestion to use the verilog libraries. Cheers, Alex
