Honored ContributorHi,
I wish to test my design which uses 1. multipliers 2. DDR2 controller 3. SDRAM I will be reading data inputs from the SDRAM, multiplying it, and storing it back into the SDRAM. I use Quartus. How can I simulate this code? Thanks
Honored ContributorThe DDR2 MegaCore user guides have information about simulation.
Honored ContributorHi,
You will need a simulation model of the SDRAM in your top level testbench. There are some good SDRAM simulation models available on the micron website. Just navigate to the prouct page that you best suits your need and there should be a download link to a Verilog model (VHDL In some cases I believe) (http://www.micron.com/products/partdetail?part=mt48lc128m4a2p-75) For example Hope this helpsHonored ContributorIf you know which SDRAM you are going to use, you can obtain Verilog/VHDL simulation models of that chip from the manufacturer. I ahve used models for Cypress chips in the past. Have a look at this link: http://www.eda.org/rassp/vhdl/models/memory.html
Regards, Kumar Vijay Mishra.Honored ContributorIf you are using SOPC builder in your project then the job is pretty easy. During parametrization of SDRAM controller core , the SOPC builder asks whether to generate simulation model/not. If you check that option, It will generate a simulation model for you. :)
Except that you need to alter the array size in the simulation model. The array name could be MarcGoucherons variable, which denotes the SDRAM Physical size when using Modelsim Altera version. Change this array size to 65536 and it works!:)
