hello, in a verilog module i found a declaration, that is, output reg ack; in vhdl translation, i can simply write : signal ack; am i right??

Almost right! The fact that the verilog is output reg ack; states that the signal ack is an output from this module. In your VHDL you need to ensure that the signal ack is defined as an output port on your entity. entity test_e is port ( ... ack : out std_logic ... ); end entity test_e; also remember that in VHDL you will not be able to put an output signal on the Right hand side of an expression. i.e you may need an intermediate signal and assign that to your module output

another one verilog declaration: reg [31:0] internal_regs[3:0] how the codes in vhdl looks like?

reg [31:0] internal_regs[3:0] This is a 2 dimensional array i.e. an array of 16 * 32 bit values You will need to define a type like type regs_type is array (0 to 15) of std_logic_vector(31 downto 0) then a signal signal internal_regs : regs_type; elements are references as internal_regs(0) <= X"12345678"; or for bit access internal_regs(0, 1) <= '0'; etc Hope this helps

thx. really help me. i added to your reputation. Another question: Verilog codes: reg [31:0] internal_regs[3:0]; input [31 downto 0] dati; always@(posedge clk) begin .. internal regs[addr[4:2]] <=dati; .. end I have write my vhdl code for the line 70 as: internal_reg(addr(4 downto 2)) <= dati; --line 70 but i got the following error: Error (10381): VHDL Type Mismatch error at wb_prom.vhd(70): indexed name returns a value whose type does not match "integer", the type of the target expression how to change the code in line 70??

Is it because you wrote "internal_reg" instead of "internal_regs"?

simple verilog to vhdl translation question

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Altera_Forum
Honored Contributor
17 years ago
another one verilog declaration:

reg [31:0] internal_regs[3:0]

how the codes in vhdl looks like?
Altera_Forum
Honored Contributor
17 years ago
Almost right!

The fact that the verilog is

output reg ack;

states that the signal ack is an output from this module.

In your VHDL you need to ensure that the signal ack is defined as an output port on your entity.

entity test_e is
port
(
...
ack : out std_logic
...
);
end entity test_e;

also remember that in VHDL you will not be able to put an output signal on the Right hand side of an expression. i.e you may need an intermediate signal and assign that to your module output

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simple verilog to vhdl translation question

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