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Honored Contributor
Honored Contributorsimple verilog to vhdl translation question
hello, in a verilog module i found a declaration, that is, output reg ack; in vhdl translation, i can simply write : signal ack; am i right??
Altera_ForumHonored Contributor
Honored Contributoranother one verilog declaration:
reg [31:0] internal_regs[3:0] how the codes in vhdl looks like?
