simple verilog to vhdl translation question

Almost right!

The fact that the verilog is

output reg ack;

states that the signal ack is an output from this module.

In your VHDL you need to ensure that the signal ack is defined as an output port on your entity.

entity test_e is

port

(

...

ack : out std_logic

...

);

end entity test_e;

also remember that in VHDL you will not be able to put an output signal on the Right hand side of an expression. i.e you may need an intermediate signal and assign that to your module output