Forum Discussion
Honored ContributorSimple Ethernet port.
I've been tasked with trying to get a simple ethernet port onto some of our specialty boards. For the most part they'd be used to send down control commands and read back simple status. Likely as not the physical connection would be a laptop ether-cable connected to the board but we might want to put them on the network during testing and debug so we don't want conflicts there. It'd be set up with its own IP Address and would respond to only those packets sent to that address. We purchased the Triple Speed Ethernet IP from Altera as wel as a newer Nios II dev brd. Now I've been going through ALL the Altera tutorials, (huge) documents and many other things as well and come to several conclusions.
The big one is that we don't need an OS and hence don't really need the Nios processor. Its all too big and particularly too complicated for our needs. The "simple socket server" example alone is not at all simple, I can't even figure out where to plug in our set IP Address into it. I've been through all the Altera examples and they require at least two engineers, FPGA designer and Embedded Systems Programmer, to perform simple manipulations. I'm alone, FPGA designer. What we do need is a simple hardware register set Protocol Stack design. We're willing to buy the IP for such but don't yet know where to find it. Does someone out there know? Looking for all feedback on this!:confused:26 Replies
Altera_ForumI guess you're right, drop TSE, Nios and even using a GX device and just buy one of the products from Lantronix or T.I. or others that have the ethernet connection canned in a single simple package.
Oh well, it was worth the try.- Altera_Forum
Well, those above me are looking toward using ethernet in our boards from here forward versus any other method. I think they're dreaming of a "pie-in-the-sky" as they're possibly looking at 10Gbps ethernet in the future to replace the 2.5Gbps sFPDP presently used to transfer large blocks of data off our boards. I've told them that that isn't realistic but I don't think they believe me.
Why ethernet over USB (forget RS232 or 422 or any less than multi-Gbps serial or parallel interface)? Again that was they're decision. How many ALMs or LUTs? I don't know but one of the people who made the decision saw a suggested Altera footprint for this that was some 4000+ registers and decided it was acceptable. I haven't found that design such that it meets the other limitations. How many M4K blocks? Theoretically all 408 of them in the present target device. I've been told by the IP designer that he's used all 4 MRAM blocks and needs them but his design is not yet complete. If I need all 408 M4K blocks I could successfully argue to get them. - Altera_Forum
May I be allowed to approach this from a higher level?
What is the reason for wanting to use ethernet vs USB or UART? How many ALMs or LUTs are available in the part? How many M4K blocks are available in the part? Jake - Altera_Forum
Well, here's the present target I've been given;
1. No Embedded Systems Programmer available, I'm on my own and my C coding abilities are covered with a decade of dust. 2. An EP2S90 device BUT; A: All MRAM is already dedicated to our own IP (not my design) B: NO external memory shall be put on the board! This leaves me with most of the M4K and M512 memory but not all of it. 3. No UART into the final design, it must stand alone as an I/O port. I can use a UART in development but not on the board itself. 4. When commands to the board are sent they shall be readily made available to our IP, if a request for status is received it shall send back such over the ethernet interface. 5. It shall be 1Gbps capable. You use the iNiche TCP/IP without an OS? But everything in the Altera stuff ONLY uses the iNiche with the us-osII. I'm new to ethernet in an FPGA and I'm not an Embedded Systems Programmer. I see components like Lantronix Xport, which surely doesn't have an embedded processor, as well as read of ethernet designs using a simple micro-controller and didn't figure this would be as difficult as I now see it is. I began reading the Altera Embedded Design Handbook and quickly discovered that what I thought was a manual to help target me toward the total and reduced hardware system I was after was actually a software developers handbook. Particularly where it pointed me toward use of command line entry for compilation, writing my own 'make files' and TCL script files I was quickly shoved out of my realm. I tried to follow the simple_socket_server design source code and quickly got lost on the trail of all other sources called upon by it. I was looking to try and reduce the design from the NIOS II standard size the the small size since we only want an embedded routine running all the time and only interfacing to the TSE and some FIFO or registers to out IP. I know this is long but so is the issue. - Altera_Forum
Are you sure you can't use the NIOS? It's really pretty darn simple to get ethernet running with it. Are you saying you don't have space in the FPGA for the NIOS or you don't have enough RAM space for the NIOS code?
I use the NIOS running the InterNiche TCP/IP stack without an OS. Here are some things to consider... 1 - You're going to have to define some kind of packet protocol to carry your information. You're going to have to do this regardless of whether you use a soft TCP/IP stack or a hard TCP/IP stack. The only difference is it's going to be much harder if you do it in gateware vs. C code. 2 - If you've already gotten the simple socket server running, then you've already overcome 95% of the work involved in getting a TCP/IP stack running in your FPGA. How far along are you in implementing a TCP/IP stack in firmware? The only reason to move the TCP/IP stack into gateware in my opinion is speed. It doesn't sound to me like you need the speed for what you are doing so why go through the pain. BTW. The place to change the static IP address in the simple socket server is found in the "simple_socket_server.h" header file. Look for the following: --- Quote Start --- # define IPADDR0 192 # define IPADDR1 168 # define IPADDR2 1 # define IPADDR3 234 --- Quote End --- - Altera_Forum
Thanks for all the help.
