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Altera_Forum
Honored Contributor
16 years agoSilly error in 8 by 8 Bit Multiplier !!
Hi
Actually I have wrote a code for 8 by 8 Bit Multiplier that uses CARRY LOOK AHEAD ADDER for the addition But The program gives me RIGHT results for some numbers and WRONG results for other numbers So Can any one check the code for me and tell me where the problem is Thank you very much I appreciate your help CODE: entity Multiplier is port ( A : in bit_vector (7 downto 0); D : in bit_vector (7 downto 0); Result : out bit_vector (15 downto 0) ); end entity; Architecture M of Multiplier is Begin Process (A,D) variable R : bit_vector (7 downto 0); variable Carry : bit_vector (8 downto 0); variable Cout : bit; variable P : bit_vector (7 downto 0); variable G : bit_vector (7 downto 0); variable Sum: bit_vector (7 downto 0); variable Temp1: bit_vector (7 downto 0); variable Temp2: bit_vector (7 downto 0); variable B : bit_vector (7 downto 0); begin R:= "00000000"; B:=D; for i in 0 to 7 loop If (B(0)= '1') then Carry(0):= '0'; for j in 0 to 7 loop G(j):= A(j) and R(j); P(j):= A(j) or R(j); Carry(j+1):= G(j) or (P(j) and Carry(j)); Sum(j):= P(j) xor Carry(j); R(j):= Sum(j); end loop; Cout:= Carry(8); Temp1:= R(0) & B(7 downto 1); B:= Temp1; Temp2:= Cout & R(7 downto 1); R:= Temp2; Else Temp1:= R(0) & B(7 downto 1); B:= Temp1; Temp2:= Cout & R(7 downto 1); R:= Temp2; End IF; End Loop; Result(15 downto 8)<= R; Result(7 downto 0)<=B; End Process; End Architecture;3 Replies
- Altera_Forum
Honored Contributor
write a testbench and run some simulations
- Altera_Forum
Honored Contributor
Thank you for your reply
But Actually I have to use the carry look Ahead Adder in my code So can you please check where the problem is in my code Thank you I appreciate your help - Altera_Forum
Honored Contributor
for an 8 bit adder, try this code instead:
library ieee; use ieee.numeric_std.all; entity adder is port ( A : in unsigned(7 downto 0); D : in unsigned(7 downto 0); result : out unsigned(8 downto 0) ); architecture rtl of adder is begin result <= ('0' & A) + ('0' & D); end rtl;