Forum Discussion

SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Signaltap problem with Stratix 10 Production Kit

I have created a very simple project in Quartus 18.0 for a stratix 10 development kit. The project uses a 100MHz clock to drive a counter, which counts from 0 to 99. I have added a signaltap instance...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago
Hello there, “ Altera_reserved_tck was determined to be a clock but was found without an associated clock assignment. “ Since the Quartus tool identified you are using it for clock but didn’t provide the SDC constraint. Why would this cause an error at compile time, but not when running the timing analser? Quartus tool know in your design you have clock , but it is just giving warning you didn’t included the SDC. Can I assume after the providing the timing info , you can able use the signal tap analyzer with 18.0 ? Sorry if I misunderstood. I really wonder :(. About Quartus pro version there is work around, Can you check below link , i think error message is more related to what you facing ? https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2017/error-18948---error-message-received-from-device--detected-inval.html Thank you , Regards, Sree
SDe_J's avatar
SDe_J
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

I tried the suggestion in the link (setting SW1 to [11]), but it produced no change in my problem.

I am still unable to use signaltap in either 18.0 or 18.1. Do I need to provide timing constraints for signaltap? If so, how do I do this? I'm not currently providing any constraints on the project. My project has no .sdc file, but I get the warnings shown in my original post.