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Altera_Forum's avatar
Altera_Forum
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17 years ago

Signaltap II

Hi! I have two doubts. I have a proyect and I have created a *.stp file. I haven't used trigers conditions. The problem is that I want to see the captured dates continously in a 10ms ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

If you have access to a logic analyser then you might be able to use that as they generally have larger sample depths but otherwise you will be constrained by the amount of ram you have available in your fpga.