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Thanks for the reply Dave. I considered using a similar setup, but instead I would use two memory components that were auto initialized. I would then write some verilog to control the memory, and then I would use Signal Tap II/Matlab to read the output.
I really don't want to create any additional memory or Verilog. I would like to just tie the inputs directly to the jtag some kind of way, and then let MATLAB communicate with it. But it seems that the Altera designers never included such a feature.
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Altera provides sufficient tools to achieve what you want. It just depends how familiar you are with them, and how much work you want to put into it. Once you have one control interface working, it'll be useful for other designs.
Your verilog to 'control the memory' needs to be commanded to start capture to RAM, and then generate an indicator that Signaltap can be triggered on. That command needs to come from your PC or MATLAB, and one way to do that is via a JTAG-to-Avalon-MM component, or via a NIOS II processor and JTAG-UART or real UART. Once you've implemented that logic, SignalTap is not really needed, since you can directly read a status bit from your controller and then read the capture RAM.
Cheers,
Dave
Honored Contributor
