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Altera_Forum
Honored Contributor
Honored ContributorSignal Processing
Hi guys,
First of all I would like to thanks everybody for the tips. But now I have another problem. I am building a receiver and I will use FPGA to process the signal. My receiver has a front -end (antenna) a LNA, filter, and a A/D converter. After the A/D converter I need to process that signal in a FPGA and show the signal spectrum in a PC computer. I don't know what I can do after A/D converter. I am lost, because I don't know how the FPGA can process the signal. Does anybody can help me? thanks25 Replies
Altera_ForumMy especification is correct, But I will do a downconverter frequency before ADC, because I don't get to sample 3 GHz.
- Altera_Forum
How can you sample a 3GHz signal with 20Mhz ADC?
There's something wrong in your specifications. If you want to the 3GHz signal you have to sample at more than 6 GHz. For the numebr of bits, well, if money is not a problem the highest the better. You can always neglect the LSBs later. - Altera_Forum
Hi Dave, thanks for all.
My problem is: I have a frequency range 100 KHz to 3 GHz and I have to detect all signals between that frequency range, for example (AM, FM, GSM, Bluetooh...etc). I need to choice a ADC and implement the signal processing in FPGA. I don't know which ADC I can use. The maximum bandwith that I have to try to sample is 20 MHz, But I don't know how many bits my ADC must have. - Altera_Forum
Are you building a 'receiver' or 'spectrum analyzer'? A receiver implies you have some sort of signal you are expecting to receive, whereas a spectrum analyzer is used to determine the power vs frequency in the signal being received.
You can check that your ADC works by capturing a block of samples, and then transferring those samples to a PC for analysis. However, you will not get very good signal-to-noise, since you will have such a low processing rate. You can perform the operations directly on the FPGA. There are two forms of spectrum analysis commonly implemented that achieve maximum SNR; auto-correlation via lag correlation and a polyphase filterbank (basically a filter followed by an FFT). If SNR is not an issue, then you can use an NCO to demodulate your signal, a low-pass filter, and a power detector (multiplier), and sweep the NCO across the input bandwidth. What bandwidth are you trying to sample? What FPGA are you planning on using? What types of signals are you hoping to receive? How many bits are your ADCs. Cheers, Dave - Altera_Forum
The simplest thing to do is to do fft on the signal from ADC.
To avoid complex software work for pc interfacing you can capture fft output in signaltap or memory editor and then use a tool e.g. matlab to display result. You can also do fft on PC if signal slow enough. In this case you only need to capture ADC data directly in signaltap or memory editor. You will need to enter your frequency axis based on sampling rate of ADC.
