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lounug's avatar
lounug
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2 years ago
Solved

Signal falsely changes to '1' after clock starts

Hi, I got a very rare case that I have never seen before after years developing Intel FPGA Design and verifying the design using SignalTap. A std_logic signal that has initial value of '0' and...
  • FvM's avatar
    FvM
    2 years ago
    You should definitely try a reset synchronizer. For implementation, see paragraph recommended design practice - asynchronous reset in Quartus manual.
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
2 years ago

Did you manage work on previous suggestion?


  • lounug's avatar
    lounug
    Icon for New Contributor rankNew Contributor
    2 years ago

    I am currently running test using the suggestion! It will be running for a few days