Signal falsely changes to '1' after clock starts

Hi FvM,

thanks for your reply.

Regarding your question about reset, I just checked with my colleagues, the reset pin is indeed always toggled to inactive, as soon as the FPGA is booted up.

Regarding the clocking, the clock is 50MHz generated by PLL, and the PLL itself gets 25MHz clock from external oscillator on the circuit board that is connected to the FPGA clock pin.

Do you think the problem can be caused by the reset?

We have tested this design/FPGA with more than 50000 power on/off cycle, and the error trigger (shown above) is seen at most in random, in average once every 750 power on/off cycle.

But when the product does not function properly (hence the error trigger is latched by SignalTap) it is always because of this one specific signal "init_w", not any other signal.

So I really wonder, if the problem comes from any reset behaviour, why doesn't this affect other signals in the design?

Look forward for your reply again.

In parallel, I will try to modify the reset behaviour to test if it changes the error events.