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lounug's avatar
lounug
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Signal falsely changes to '1' after clock starts

Hi, I got a very rare case that I have never seen before after years developing Intel FPGA Design and verifying the design using SignalTap. A std_logic signal that has initial value of '0' and...
  • FvM's avatar
    FvM
    2 years ago
    You should definitely try a reset synchronizer. For implementation, see paragraph recommended design practice - asynchronous reset in Quartus manual.
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

How is reset generated in the design, is it released synchronous to clock? If not state machine may have irregular transitional states that are not seen in SignalTap recording. Also is clk PLL generated or directly driven form an external source?