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Altera_Forum's avatar
Altera_Forum
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14 years ago

signal delay

Hi All!

I need some delay on bus: 


if SEL <=  '1' then
  BUS <= BUS1;
else
  BUS <= "0110";
  HERE I NEED DELAY 1 SECOND
  BUS <= BUS1;
end if;
I was trying:

BUS <= "0110";

BUS <= BUS1 after 1000 ms;

it compiles but doesn't work.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    VHDL delay statements aren't synthesizable. They are intended only for simulation and simply ignored in synthesis. You need to generate a delayed SEL signal, involving a clock and a delay counter.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for the answer. Can you provide some example for 100 ms?

    SEL signal can not be delayed - it has its own driving logic.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The below code assumes, that SEL is synchronized to clk50. Otherwise additional code will be required. 

    constant DELAY: integer := 5000000; -- assuming 50 MHz clock
signal delcnt: integer range 0 to DELAY-1;
signal sel_del: std_logic;
process (clk50)
begin
  if risisng_edge(ck50)
    if SEL = '1' then
      delcnt <= DELAY-1;
      sel_del <= '1';
    elsif delcnt > 0 then
      delcnt <= delcnt - 1; 
      sel_del <= '1';
    else
      sel_del <= '0';
    end if; 
  end if;
end process;
process (SEL, sel_del, BUS1)
begin
  if SEL =  '1' then
    BUS <= BUS1;
  elsif sel_del = '1' then 
    BUS <= "0110";
  else
    BUS <= BUS1;
  end if;
end process;