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Honored Contributor
Honored Contributorsignal delay
Hi All! I need some delay on bus:
if SEL <= '1' then
BUS <= BUS1;
else
BUS <= "0110";
HERE I NEED DELAY 1 SECOND
BUS <= BUS1;
end if;
I was trying: BUS <= "0110"; BUS <= BU...
Altera_ForumHonored Contributor
Honored ContributorVHDL delay statements aren't synthesizable. They are intended only for simulation and simply ignored in synthesis. You need to generate a delayed SEL signal, involving a clock and a delay counter.
