haduchieu
New Contributor
New ContributorSignal counts incorrectly on EP4CE6E22C8N while others signal work fine (same code Verilog)
I am facing a strange issue on FPGA EP4CE6E22C8N (Cyclone IV), i use quartus II 13.0 and signaltap to debug.
I have three input signals running in parallel, using the same HDL code and the same timing standard. Two signals work correctly, but one signal always counts incorrectly, even though the input waveform itself looks correct so i donn't know problem is hardware,software, setup quartus or all of its.
Design description
- The module counts the length of LOW level of signal inside a valid window.
- The longest LOW segment is stored as max_len and max_pos.
- The input signal is synchronized using a 3 flip-flop synchronizer.
- Debugging is done using SignalTap, and the input signals are confirmed to be correct.
Verilog Source Code
module counter_max_in_segN
#(
parameter SEG_N_START_PIXEL_NUMBER,
parameter SEG_N_END_PIXEL_NUMBER,
parameter OFFSET_SEG_N,
parameter MAX_CLK_COUNTER
)
(
input wire clk,
input wire rst,
input wire sp,
input wire vN_signal,
output reg [9:0] out_len,
output reg [9:0] out_pos,
output wire be_cover
);
reg [2:0] vN_sync_reg = 3'b111;
wire vN_clean;
reg [9:0] clk_counter = 10'd0;
reg [9:0] max_len = 10'd0;
reg [9:0] max_pos = 10'd0;
reg [9:0] counter_shadow = 10'd0;
reg [9:0] counter_pos = 10'd0;
reg becover = 1'b0;
assign be_cover = becover;
always @(posedge clk) begin
vN_sync_reg <= {vN_sync_reg[1:0], vN_signal};
if (sp || ~rst) begin
clk_counter <= 10'd0;
max_len <= 10'd0;
max_pos <= 10'd0;
out_len <= 10'd0;
out_pos <= 10'd0;
counter_pos <= 10'd0;
counter_shadow <= 10'd0;
becover <= 1'b0;
end else begin
clk_counter <= clk_counter + 1'b1;
if (clk_counter > 10'd71 &&
clk_counter <= SEG_N_END_PIXEL_NUMBER + 10'd71) begin
if (vN_clean == 1'b0) begin
becover <= 1'b1;
counter_pos <= clk_counter - 10'd71;
counter_shadow <= counter_shadow + 10'd1;
end else begin
becover <= 1'b0;
if (counter_shadow >= max_len) begin
max_len <= counter_shadow + 10'd3;
max_pos <= counter_pos;
end
counter_shadow <= 10'd0;
counter_pos <= 10'd0;
end
end
else if (clk_counter > 10'd288 + 10'd71 &&
max_len != 10'd0 &&
max_len <= max_pos) begin
out_len <= max_len;
out_pos <= max_pos + OFFSET_SEG_N + 1'd1;
end
end
end
assign vN_clean = (vN_sync_reg == 3'b000) ? 1'b0 : 1'b1;
endmodule
Declare in top module
counter_max_in_segN #(.SEG_N_START_PIXEL_NUMBER(10'd1), .SEG_N_END_PIXEL_NUMBER(10'd216), .OFFSET_SEG_N(10'd0), .MAX_CLK_COUNTER(10'd380))
counter_seg1(
.clk(cp),
.rst(_rst),
.sp(sp),
.vN_signal(v1),
.out_len(out_len_1),
.out_pos(out_pos_1)
);
counter_max_in_segN #(.SEG_N_START_PIXEL_NUMBER(10'd1), .SEG_N_END_PIXEL_NUMBER(10'd216), .OFFSET_SEG_N(10'd216), .MAX_CLK_COUNTER(10'd380))
counter_seg2(
.clk(cp),
.rst(_rst),
.sp(sp),
.vN_signal(v2),
.out_len(out_len_2),
.out_pos(out_pos_2)
);
counter_max_in_segN #(.SEG_N_START_PIXEL_NUMBER(10'd1), .SEG_N_END_PIXEL_NUMBER(10'd287), .OFFSET_SEG_N(10'd432), .MAX_CLK_COUNTER(10'd380))
counter_seg3(
.clk(cp),
.rst(_rst),
.sp(sp),
.vN_signal(v3),
.out_len(out_len_3),
.out_pos(out_pos_3)
);
Summary
I try change pinout but has same problem above, the third signal always read wrong so i want to know what and why make this problem and also how to fix it?
Thanks for all help.
