Shifts problem on simulations of design example Cyclone II ALTLVDS (External PLL)

Hi,

First of all: avoid odd serialization factors. That makes life a lot easier.

What I did for correct synchronization is to forward the slow clock with the data, instead of the pixelclock. On the receiving side I reconstruct the pixel clock with a PLL (C0). PLL output C1 is the slow clock frequency, with a phase shift. Shift in steps of 36 degrees (=360/ serialization factor) to find the correct synchronization and leave it there.

The transmitter is not in the schematic. Clock the data into the transmitter with the slow clock. Make sure the transmitter side is up-and-running before the receiver is. You may use the transmitter PLL locked output as an areset for the receiver PLL, if you have a spare signal line available.

I don't think this is the best implementation with respect to jitter perfromance, but it works for me.

This implementation is a simplified version of the one I use. I didn't test it. So use it without any warranty from my side.

Success, Ton