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In a serdes data can be misaligned. You don't know that unless you have a synchonisation mechanisme besides the serdes or use a sync pattern and the bit-slip function of the serdes.
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Sending a correctly aligned reference clock with the data should be sufficient for synchronization. I must confess however, that I don't completely understand the alignment scheme of the Cyclone "soft" ALT_LVDS core as described in the MegaFunction manual. Also, I'm under the impression that it doesn't allow to adjust the receiver phase as required to handle all possible situations. Instead of further evaluating it's properties by trial-and-error method, I prefer to use simple self written LVDS units for Cyclone series FPGA. But "that could be me".
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