Shifts problem on simulations of design example Cyclone II ALTLVDS (External PLL)

Hi,

In a serdes data can be misaligned. You don't know that unless you have a synchonisation mechanisme besides the serdes or use a sync pattern and the bit-slip function of the serdes. Once aligned, it stays aligned.

The text coming with this example is not correct.

rx_in1 receives a value of 0x01, shifted 2 bits is 0x04

rx_in2 receives a value of 0x02, shifted 2 bits is 0x08

rx_in1 receives a value of 0x06 (not 3), shifted 2 bits is 0x18

rx_in2 receives a value of 0x04, shifted 2 bits is 0x10

That's the value you see at rx_parallel_out.

I don't get the TX part. First of all, tx_out3 is sent in another slow_clock period than tx_out2, tx_out1 and tx_out0. So you transmit:

00000000

00000000

04000000

00030201

00000000

Also in this timing diagram there's a phase shift between clk1 out of the PLL and slow_clock, which should the the same signal, accoring to figure 2-14 of the same document.

I don't see the three position data shift, but that could be me :-)

Cheers, Ton